;MACHXL Design Description ;---------------------------------- Declaration Segment ------------ TITLE Super PLA - all Commodore 82S100 replacement PATTERN none REVISION V1.0 AUTHOR Jens Schoenfeld COMPANY individual Computers DATE 06/02/02 CHIP _PLA MACH110 ;---------------------------------- PIN Declarations --------------- ;inputs PIN 33 I8 PIN 24 I9 PIN 31 I10 PIN 14 I11 PIN 30 I12 PIN 15 I13 PIN 16 I15 PIN 29 I14 PIN 37 I7 PIN 11 I6 PIN 2 I5 PIN 38 I4 PIN 39 I3 PIN 43 I2 PIN 9 I1 PIN 7 I0 ;outputs PIN 18 F3 PIN 21 F2 PIN 17 F1 PIN 27 F0 PIN 6 F6 PIN 3 F7 PIN 8 F5 PIN 4 F4 NODE ? F1low NODE ? F6low NODE ? F7low NODE ? NoC64Ram NODE ? CasRam ;----------------------------------- Boolean Equation Segment ------ EQUATIONS ;jumper settings ([0],[1],[2]): ; 000 = C16/C116/Plus 4 PLA ; 100 = Floppy 1551 cartridge PLA ; 010 = C610 PLA ; 110 = C710 PLA ; 001 = C64 PLA minimize_off /F0 =/CasRam ;F1 = F1low /F2= I5*I6*I7*I2*I13*/I10*I11 +I5*I6*I7*I2*/I13*/I12*/I10*I11 /F3 = I5*I6*/I7*I8*/I3*/I2*I1*I13*/I10*I11 +I5*I6*/I7*I8*/I3*I2*I13*/I10*I11 +I5*I6*/I7*I8*/I3*I2*/I13*/I12*/I10*I11 +I10*I12* I13*I4*/I14*I15 +I10*/I12*I4*/I14*I15 /F4= /I0 * I5 * I6 */I7*I8*/I10*/I11 /F5=I5*I6*/I7*I8*I3*I1*/I2*/I10*/I11 +I5*I6*/I7*I8*I3*I2*/I10*/I11 +I5*I6*/I7*I8*I12*/I13*/I10*/I11 +I5*I6*/I7*I8*I3*I1*/I2*/I10*I11*I9 +I5*I6*/I7*I8*I3*I2*/I10*I11*I9 +I5*I6*/I7*I8*I12*/I13*/I10*I11*I9 ;F6 = F6low ;F7 = F7low /F1 =I5*/I6*I7*I1*I2*I13*/I10*I11;war:low /F7= I5*/I6*I7*/I10*I11*I2*/I12*/I13 +I5*I6*I7*/I10*/I13*I12 +I15*I14*I10*/I13*I12 /F6 = I5*/I6*/I7*/I10*I11*/I12*I1*I2 +I5*/I6*/I7*/I10 *I12*/I13 NoC64Ram =F5*F7*F6*F3*F1*F2 CasRam= /NoC64Ram + I0 + /I0 * I12 * /I13 * /I5 * I6 + /I0 * I12 * /I13 * /I6 * I7 + /I0 * I12 * /I13 * /I5 */I6*/I7*I8 + /I0 * I12 * /I13 * I5 * I6*/I7*/I8 ;----------------------------------- Simulation Segment ------------ SIMULATION ;-------------------------------------------------------------------